1) Field of the Invention
This invention relates generally to fabrication of MOS semiconductor devicesland more particularly to the fabrication of a self aligned elevated S/D for a MOS Transistor.
2) Description of the Prior Art
As devices are scaled down, source/drain (S/D) formation needs to be improved in order to avoid junction leakage due to the shallow junction and the salicide formation.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,422,289 (Pierce) shows elevated S/D formed by CMP a poly layer.
U.S. Pat. No. 6,015,727 (Wanlass) shows a damascene process for Poly S/D contacts and Gate.
U.S. Pat. No. 5,804,846 (Fuller) teaches a method for a self aligned elevated S/D by W layer and CMP.
However, better isolation for elevated source/drain (S/D) regions is still required.
It is an object of the present invention to provide a method for fabricating a MOS transistor with elevated S/D regions that has reduced junction leakage.
It is an object of the present invention to provide a method for fabricating a MOS transistor with elevated S/D regions that are formed over an S/D insulating layer.
It is an object of the present invention to provide a method for fabricating a MOS transistor with elevated S/D regions that are salicided.
It is an object of the present invention to provide a method for fabricating a MOS transistor with elevated S/D regions that has improved hot carrier integrity.
To accomplish the above objectives, the present invention provides a method for a self aligned transitor with elevated S/D regions on an insulated oxide by forming a trench along side the STI and filling the trench with oxide. There are two preferred embodiment of the invention.
The method can be described as follows. STI regions are formed in a substrate. Next, we form a gate structure. The gate structure is preferably comprised of: a gate dielectric layer, a gate, and a hard mask. We then form LDD regions adjacent to the gate structure in the substrate. We form first spacers on the sidewall of the gate structure. We etch S/D trenches between the STI regions and the first spacers. The S/D trenches are filled with a S/D insulating layer.
The first and second preferred embodiment shows different method for performing the remaining steps. Next, we form elevated S/D regions over the S/D insulating layer and the LDD regions. We also, form a top isolation layer over the STI regions.
The invention has many advantages over the prior arts. The invention effectively isolated the raised source/drain (S/D) regions from the other elements and reduces junction leakage. The invention particularly improves junction leakage in Transistors with salicide processes as the salicide and silicon interface is placed away from the elevated S/D junction.
The invention reduces the hot carrier degradation to the gate oxide as the peak electric field is reduced.
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the append claims.